library verilog;
use verilog.vl_types.all;
entity total_vlg_check_tst is
    port(
        h               : in     vl_logic_vector(3 downto 0);
        l               : in     vl_logic_vector(3 downto 0);
        out1            : in     vl_logic_vector(6 downto 0);
        out2            : in     vl_logic_vector(6 downto 0);
        sampler_rx      : in     vl_logic
    );
end total_vlg_check_tst;
